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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. october 1995 copyright ? intel corporation, 1996 order number: 281630-001 82595TX isa/pcmcia high integration ethernet controller y optimal integration for lowest cost solution e glueless 8-bit/16-bit isa/pcmcia 2.0 bus interface e provides fully 802.3 compliant aui and tpe serial interface e local dram support up to 64 kbytes e flash/eprom boot support up to 1 mbyte for diskless workstations e hardware and software portable between motherboard, adapter, and pcmcia lan card solution y high performance networking functions e concurrent processing functionality for enhanced performance e 16-bit/32-bit io accesses to local dram with zero added wait-states e ring buffer structure for continuous frame reception and transmit chaining e automatic retransmission on collision e automatically corrects tpe polarity switching problems y low power chmos iv technology y ease of use e integrated plug n' play tm hardware functionality e eeprom interface to support jumperless designs e software structures optimized to reduce processing steps e automatically maps into unused pc io locations to help eliminate lan setup problems e all software structures contained in one 16-byte io space e jtag port for reduced board testing times e automatic or manual switching between tpe and aui ports y power management e sl compatible smout power down input e software power down command for non-sl systems y 144-lead tqfp package provides smallest available form factor y 100% backwards hardware/software compatible to 82595 281630 1 figure 1. 82595TX block diagram
82595TX isa/pcmcia high integration ethernet controller contents page 1.0 introduction 5 1.1 82595TX overview 5 1.2 enhancements to the 82595 5 1.3 compliance to industry standards 5 1.3.1 bus interfaceeisa ieee p996/pcmcia 2.0 6 1.3.2 ethernet/twisted pair ethernet interfaceeieee 802.36 specification 6 2.0 82595TX pin definitions 6 2.1 isa bus interface 6 2.2 pcmcia bus interface 8 2.3 local memory interface 9 2.4 miscellaneous control 11 2.5 jtag control 11 2.6 serial interface 12 2.7 power and ground 13 2.8 82595TX pin summary 14 3.0 82595TX internal architecture overview 15 3.1 system interface overview 15 3.1.1 concurrent processing functionality 15 3.2 local memory interface 15 3.3 csma/cd unit 16 3.4 serial interface 16 4.0 accessing the 82595TX 16 4.1 82595TX register map 16 4.1.1 io bank 0 17 4.1.2 io bank 1 18 4.1.3 io bank 2 19 4.2 writing to the 82595TX 19 4.3 reading from the 82595TX 20 contents page 4.4 local dram accesses 20 4.4.1 writing to local memory 20 4.4.2 reading from local memory 20 4.5 serial eeprom interface 21 4.6 boot eprom/flash interface 22 4.7 ia prom interface 22 4.8 pcmcia cis structures 22 4.9 pcmcia decode functions 22 5.0 command and status interface 23 5.1 command op code field 23 5.2 abort (bit 5) 23 5.3 pointer field (bits 6 and 7) 23 5.4 82595TX status interface 24 6.0 initialization 24 7.0 frame transmission 25 7.1 82595TX xmt block memory format 25 7.2 xmt chaining 27 7.3 automatic retransmission on collision 30 8.0 frame reception 30 8.1 82595TX rcv memory structure 30 8.2 rcv ring buffer operation 33 9.0 serial interface 34 10.0 application notes 35 10.1 bus interface 35 10.2 local memory interface 35 10.3 eeprom interface (isa only) 35 10.4 serial interface 35 10.4.1 aui circuit 35 10.4.2 tpe circuit 35 10.4.3 led circuit 36 2
contents page 10.5 layout guidelines 36 10.5.1 general 36 10.5.2 crystal 36 10.5.3 82595TX analog differential signals 36 10.5.4 decoupling considerations 36 11.0 electrical specifications and timings 37 11.1 absolute maximum ratings 37 11.1.1 package thermal specifications 38 contents page 11.2 a.c. timing characteristics 38 11.3 a.c. measurement conditions 38 11.4 isa interface timing 39 11.5 pcmcia interface timing 44 11.6 local memory timings 47 11.6.1 dram timings 47 11.6.2 flash/eprom timings 49 11.6.3 ia prom timings 51 11.7 interrupt timing 52 11.8 reset and smout timing 52 11.9 jtag timing 53 11.10 serial timings 54 3
82595TX 281630 2 figure 2. 82595TX pinout 4
82595TX 1.0 introduction 1.1 82595TX overview the 82595TX is a highly integrated, high perform- ance lan controller which provides a cost effective lan solution for isa compatible personal computer (pc) motherboards (both desktop and portable), add-on isa adapter boards, and pcmcia cards. the 82595TX integrates all of the major functions of a buffered lan solution into one chip with the excep- tion of the local buffer memory, which is implement- ed by adding one dram component to the lan so- lution. the 82595TX's new concurrent processing feature significantly enhances throughput perform- ance. both system bus and serial link activities occur concurrently, allowing the 82595TX to maximize net- work bandwidth by minimizing delays associated with transmit or receiving frames. the 82595TX's bus interface is a glueless attachment to either an isa or pcmcia version 2.0 bus. its serial interface provides a twisted pair ethernet (tpe) and an at- tachment unit interface (aui) connection. by inte- grating the majority of the lan solution functions into one cost effective component, production cost saving can be achieved as well as significantly de- creasing the design time for a solution. this level of integration also allows an 82595TX solution to be ported between different applications (pc mother- boards, adapters, and pcmcia io cards), while maintaining a compatible hardware and software base. this results in further savings in both hardware and software development costs for manufacturers expanding into different applications i.e., an isa adapter vendor producing pcmcia io cards, etc. the 82595TX's software interface is optimized to re- duce the number of processing steps that are re- quired to interface to the 82595TX solution. the 82595TX's initialization and control registers are di- rectly addressable within one 16-byte io address block. the 82595TX can automatically resolve any conflicts to an io block by moving its io offset to an unused location in the case that a conflict occurs. the 82595TX's local memory is arranged in a simple ring buffer structure for efficient transfer of transmit and receive packets. the local memory, up to 64 kbytes of dram, resides as either a 16-bit or 32- bit io port in the host systems io map programma- ble through configuration. the 82595TX provides di- rect control over the local dram, including refresh. the 82595TX performs a prefetch to the dram memory allowing cpu io cycles to this data with no added wait-states. the 82595TX also provides an interface to up to 1 mbyte of flash or eprom memory. an interface to an eeprom, which holds solution configuration values and can also contain the node id, allows for the implementation of a ``jumperless'' design. in addition, the 82595TX con- tains full hardware support for the implementation of the isa plug n' play specification. plug n' play elimi- nates jumpers and complicated setup utilities by al- lowing peripheral functions to be added to a pc au- tomatically (such as adapter cards) without the need to individually configure each parameter (e.g. inter- rupt, io address, etc). this allows for configuration ease-of-use, which results in minimal time associat- ed with installation. the 82595TX's packaging and power management features are designed to consume minimal board real estate and system power. this is required for applications such as portable pc motherboard de- signs and pcmcia cards which require a solution with very low real estate and power consumption. the 82595TX package is a 144-lead tqfp (thin quad flat pack). its dimensions are 20 mm by 20 mm, and 1.7 mm in height (roughly the same area as a us nickel, and the same height as a us dime). the 82595TX contains two power down modes; an sl compatible power down mode which utilizes the sl smout input, and a power down command for non-sl systems. 1.2 enhancements to the 82595 the 82595TX is fully backwards compatible to the 82595, both in pinout and software. however, the 82595TX contains several advanced functions from the 82595 which increase performance and ease of use. the following is a list of the major enhance- ments to the 82595TX: concurrent processing functionality 32-bit local memory io port integrated plug n' play support added eeprom interface for plug n' play flash addressing up to 1 mbyte (versus 256k for 82595) for further information on these enhancements and a description of all the differences between the 82595 and 82595TX, please consult the 82595TX user's manual, available through your local sales representative. 1.3 compliance to industry standards the 82595TX has two interfaces; the host system interface, which is an isa or pcmcia bus interface, and the serial, or network interface. both interfaces have been standardized by the ieee. 5
82595TX 1.3.1 bus interfacee isa ieee p996/pcmcia 2.0 the 82595TX implements the full isa bus interface. it is compatible with the ieee spec p996. the 82595TX also interfaces to isa bus implementations that deviate from the ieee spec by requiring early assertion of the iochrdy signal and alternate host address decode timing. this alternate timing can be configured in the 82595TX after a software test which is run at initialization time. the 82595TX can also be configured for a pcmcia bus interface de- pending on the state of the pcmcia/isa input pin. in this case the 82595TX implements the complete pcmcia interface, compatible to the pcmcia revi- sion 2.0 specification. 1.3.2 ethernet/twisted pair ethernet interfaceeieee 802.3 specification the 82595TX's serial interface provides either an aui port interface or a twisted pair ethernet (tpe) interface. the aui port can be connected to an ethernet transceiver cable drop, providing a fully compliant ieee 802.3 aui interface. the tpe port provides a fully compliant ieee 10base-t interface. the 82595TX can automatically switch to whichever port (tpe or aui) is active. 2.0 82595TX pin definitions 2.1 isa bus interface the isa bus interface consists of three sections: an address bus, a data bus, and a control section. symbol pin type name and function no. sa0 66 i address bus: these pins provide address decoding for up to 1 kbyte of address. these pins also provide 4 kbytes of io addressing to support the sa1 67 plug n' play standard. sa2 68 sa3 69 sa4 70 sa5 71 sa6 73 sa7 74 sa8 75 sa9 76 sa10 13 sa11 143 sa14 77 i address bus: these pins provide address decoding between the 16 kbyte and 1 mbyte memory space. this allows for decoding of a boot eprom or a sa15 78 flash in 16k increments. sa16 79 sa17 80 sa18 81 sa19 82 6
82595TX 2.1 isa bus interface (continued) symbol pin type name and function no. sd0 46 i/o data bus: this is the data interface between the 82595TX and the host system. this data is buffered by one (8-bit design) or two (16-bit design) sd1 47 transceivers. the 82595TX's data lines should always be connected to sd2 48 the b side of the data bus transceiver. sd3 49 sd4 52 sd5 53 sd6 54 sd7 55 sd8 56 sd9 57 sd10 58 sd11 59 sd12 62 sd13 63 sd14 64 sd15 65 aen 20 i address enable: active high signal indicates a dma cycle is active. bale 21 i buffered address latch enable: falling edge used to latch a valid system address. smemr 14 i memory read for system memory accesses below 1 mbyte. active low. smemw 15 i memory write for system memory accesses below 1 mbyte. active low. memr /16i memory read for system memory accesses above or below 1 mbyte. active low. this pin also determines if the 82595TX is operating in an 8- or 8/16 detect 16-bit system. for 16-bit systems, it should always be connected. memw 17 i memory write for system memory accesses above or below 1 mbyte. active low. ior 18 i io read: active low. iow 19 i io write: active low. iocs16 40 o io chip select 16: active low, open drain output which indicates that an io cycle access to the 82595TX solution is 16-bit wide. driven for io cycles to the local memory or to the 82595TX. iochrdy 37 o io channel ready: active high, open drain output. when driven low, it extends host cycles to the 82595TX solution. sbhe 32 i system bus high enable: active low input indicates a data transfer on the high byte (d8 d15) of the system bus (a 16-bit transfer). int0 26 o 82595TX interrupt 0 4: one of these five pins is selected to be active at a time (the other four are in hi-z state) by configuration. these active int1 27 high outputs serve as interrupts to the host system. int2 28 int3 29 int4 30 reset drv 12 i reset drive: active high reset signal. 7
82595TX 2.2 pcmcia bus interface the pcmcia bus interface consists of three sections: an address bus, a data bus, and a control section. symbol pin type name and function no. a0 66 i address bus: these pins provide io address decoding for up to 1 kbyte. a1 67 a2 68 a3 69 a4 70 a5 71 a6 73 a7 74 a8 75 a9 76 d0 46 i/o data bus: this is the data interface between the 82595TX and the host system. d1 47 d2 48 d3 49 d4 52 d5 53 d6 54 d7 55 d8 56 d9 57 d10 58 d11 59 d12 62 d13 63 d14 64 d15 65 8
82595TX 2.2 pcmcia bus interface (continued) symbol pin type name and function no. oe 14 i output enable (memory read): active low. we 15 i write enable (memory write): active low. iord 18 i io read: active low. iowr 19 i io write: active low. iois16 40 o io is 16: active low output which indicates that an io cycle access to the 82595TX solution is 16-bit wide. iois16 should be asserted prior to card enable or cmd (iord or iowr ) assertion. wait 37 o wait: active low output when driven low, extends host cycles to the 82595TX. ireq 26 o 82595TX interrupt: active low output. reset 12 i reset: active high reset signal. ce1 81 i card enable 1 and card enable 2: active low signals driven by the host. these signals provide a card select based on an address decode (decode ce2 82 done by the host) and also byte lane enables. when both ce1 and ce2 are high, no host accesses are made to the card. if ce1 is low (active) and ce2 is high (inactive), the device operates in byte access mode with valid data being driven on d0 d7, and a0 determines the selection of an odd or even byte. when both ce1 and ce2 are low, a word access is taking place. in this case a0 is ignored, and the data is transferred on d0 d15. odd-byte-only accesses can occur when ce1 is high and ce2 is low. in this case the data is driven on d8 d15 and a0 is ignored. see section 4.9 for a summary of the pcmcia decode functions. reg 80 i reg : is an active low input used to determine whether a host access is to attribute memory (the 1st 1k of flash or conf regs) or to common memory (flash above 1k). if reg is low the access is to attribute memory, if reg is high the access is to common memory. reg is also asserted low for all accesses to the 82595TX's io registers (including the access to the local dram via the 82595TX's local memory io port). see section 4.9 for a summary of the pcmcia decode functions. event 32 o event : is an active low output which, when enabled, will be asserted whenever a frame has been received by the 82595TX. this allows the 82595TX to ``wake up'' a system which has powered down (with the exception of powering down the lan). this output will remain asserted until the 82595TX's rcv interrupt (for the frame which woke up the system) has been acknowledged. 2.3 local memory interface symbol pin type name and function no. maddr0 126 o local memory address (maddr0 maddr8): these outputs contain the multiplexed address for the local dram. maddr1 127 maddr2 128 maddr3 129 maddr4 130 maddr5 132 maddr6 133 maddr7 134 maddr8 135 9
82595TX 2.3 local memory interface (continued) symbol pin type name and function no. mdata0 120 i/o local data bus (mdata0 mdata3): the four i/o signals, comprising the local data bus, are used to read or write data to mdata1 121 or from the 4-bit wide dram. these signals also provide the mdata2 122 lower 4 bits of data for accesses to an 8-bit flash/eprom or mdata3 123 ia prom if these components are used. a 3.3k pull-up resistor connects to mdata3 and enables eeprom port 2. ras 9 o this active low output is the row address strobe signal to the dram. cas 6 o this active low output is the column address strobe signal to the dram. lwe 1 o this active low output is the write enable to the dram. faddr14 126 o flash address 14 17 : these pins control the flash addressing from 16k to 1m to allow paging of the flash in 16k faddr15 127 spaces. these addresses are under direct control of the flash faddr16 128 paging configuration register. faddr17 129 note: isa bus i/f only faddr18 6 faddr19 31 foe 130 o this output provides the active low output enable control to the flash. fwe 1 o this output provides the active low write enable control to the flash. bootcs 141 o boot eprom/flash cs iapromcs 143 o ia prom cs fl/iadata4 132 i/o provides the upper 4 bits of an 8 bit data path for both the boot eprom/flash and ia prom, for cpu accesses. a 3.3k pull- fl/iadata5 133 down resistor connected to fl/iadata4 and a 3.3k pull-up fl/iadata6 134 resistor connected to fl/iadata7 enables autoflash/boot fl/iadata7 135 eprom detect. eepromcs 139 i/o eeprom cs: active high signal. if no eeprom is connected, this pin should be connected to v cc . in this case it will function as an input to the 82595TX to indicate no eeprom is connected. eepromsk o eeprom shift clock: this output is used to shift data into and out of the serial eeprom. port 1 (eeprom1sk) 120 port 2 (eeprom2sk) 105 note: port 2 must be used for plug n' play eepromdo i eeprom data out port 1 (eeprom1do) 121 port 2 (eeprom2do) 107 note: port 2 must be used for plug n' play eepromdi o eeprom data in port 1 (eeprom1di) 122 port 2 (eeprom1di) 106 note: port 2 must be used for plug n' play 10
82595TX 2.4 miscellaneous control symbol pin type name and function no. dirl 42 o direction low: controls the direction of the low byte data bus transceiver. the direction defaults to always point in from the isa bus to the 82595TX (dirl e 1). this direction is turned around (82595TX out to isa bus, dirl e 0) only in the case of a read access to the 82595TX based solution. dirh 45 o direction high: controls the direction of the high byte data bus transceiver. the direction defaults to always point in from the isa bus to the 82595TX (dirh e 1). this direction is turned around (82595TX out to isa bus, dirh e 0) only in the case of a read access to the 82595TX based solution. this signal is active for 16-bit accesses only. smout 11 i/o this active low signal, when asserted, places the 82595TX into a power down mode. the 82595TX will remain in power down mode until smout is unasserted. if this line is unconnected to smout from the system bus, it can be used as an active low output which, when a power down command is issued to the 82595TX, can be used to power down other external components (this output function is enabled by configuration). pcmcia/isa 22 i this pin, when strapped low, selects an isa bus interface. strapped high selects pcmcia. j0 107 i jumper: input for selecting between 7 isa io spaces (also selects whether the io location should be read from the eeprom). these pins j1 106 i/o should be connected to either v cc or gnd. the 82595TX reads the j2 105 i/o jumper block during its initialization sequence. j0 j1 j2 io address gnd gnd gnd address contained in eeprom v cc gnd gnd 2a0h gnd v cc gnd 280h v cc v cc gnd 340h gnd gnd v cc 300h v cc gnd v cc 360h gnd v cc v cc 350h v cc v cc v cc 330h 2.5 jtag control symbol pin type name and function no. tdo 97 o jtag test data out tms 98 i jtag test mode select tck 99 i jtag test clock tdi 100 i jtag test data in 11
82595TX 2.6 serial interface symbol pin type name and function no. trmt 110 o positive side of the differential output driver pair that drives 10 mb/s manchester encoded data on the trmt pair of the aui cable (data out a). trmt 111 o negative side of the differential output driver pair that drives 10 mb/s manchester encoded data on the trmt pair of the aui cable (data out b). rcv 103 i the positive input to a differential amplifier connected to the rcv pair of the aui cable (data in a). it is driven with 10 mb/s manchester encoded data. rcv 104 i the negative input to a differential amplifier connected to the rcv pair of the aui cable (data in b). it is driven with 10 mb/s manchester encoded data. clsn 112 i the positive input to a differential amplifier connected to the clsn pair of the aui cable (collision in a). clsn 113 i the negative input to a differential amplifier connected to the clsn pair of the aui cable (collision in b). tdh 93 o transmit data high: active high manchester encoded data to be transmitted onto the twisted pair. this signal is used in conjunction with tdl, tdh , and tdl to generate the pre-conditioned twisted pair output waveform. tdl 94 o transmit data low: twisted pair output driver. active high manchester encoded data with embedded pre-distortion information to be transmitted onto the twisted pair. this signal is used in conjunction with tdh, tdh , and tdl to generate the pre-conditioned twisted pair output waveform. tdh 91 o transmit data high invert: twisted pair output driver. active low manchester encoded data to be transmitted onto the twisted pair. this signal is used in conjunction with tdl, tdh, and tdl to generate the pre- conditioned twisted pair output waveform. tdl 92 o transmit data low invert: twisted pair output driver. active low manchester encoded data with embedded pre-distortion information to be transmitted onto the twisted pair. this signal is used in conjunction with tdl, tdh, and tdh to generate the pre-conditioned twisted pair output waveform. rd 102 i active high manchester encoded data received from the twisted pair. rd 101 i active low manchester encoded data received from the twisted pair. x1 115 i 20 mhz crystal input: this pin can be driven with an external mos level clock when x2 is left floating. this input provides the timing for all of the 82595TX functional blocks. x2 116 o 20 mhz crystal output: if x1 is driven with an external mos level clock, x2 should be left floating. 12
82595TX 2.6 serial interface (continued) symbol pin type name and function no. aui led/bnc dis 83 o aui led indicator: this output, when the 82595TX is used for as a tpe/aui solution, will turn on an led when the 82595TX is actively interfaced to its aui serial port. when the 82595TX is used as a bnc/aui solution, this output becomes the bnc dis output, which can be used to power down the bnc transceiver section (the transceiver and the dc to dc converter) of the solution when the bnc port is unconnected. liled 86 o link integrity led: normally on (low) ouput which indicates a good link integrity status when the 82595TX is connected to an active tpe port. this output will remain on when the link integrity function has been disabled. it turns off (driven high) when link integrity fails, or when the 82595TX is actively interfaced to an aui port. the minimum off time is 100 ms. actled 85 o link activity led: normally off (high) output turns on to indicate activity for transmission, reception, or collision. flashes at a rate dependent on the level of activity on the link. poled 84 o polarity led: if the 82595TX detects that the receive tpe wires are reversed, poled will turn on (low) to indicate the fault. poled remains on even if automatic polarity correction is enabled, and the 82595TX has automatically corrected for the reversed wires. 2.7 power and ground symbol pin type name and function no. v cc 3, 4, i power : a 5v g 5%. 8, 23, 25, 35, 38, 41, 44, 51, 61, 87, 89, 95, 109, 117, 119, 125, 136, 142 v ss 2, 5, 7, i ground : 0v. 10, 24, 33, 34, 36, 39, 43, 50 60, 72, 88, 90, 96, 108, 114, 118, 124, 131, 138, 140, 144 13
82595TX 2.8 82595TX pin summary isa/pcmcia bus interface isa muxed pin p-down pin name pcmcia type state pin name sa0 sa11 (in) a0 a9 (in) inactive sa14 16 (in) inactive sa17 (in) reg (in) inactive/act (1) sa18 (in) ce1 (in) inactive/act (1) sa19 (in) ce2 (in) inactive sd0 sd15 (i/o) d0 d15 (i/o) ts ts smemr (in) oe (in) inactive smemw (in) we (in) inactive ior (in) iord (in) inactive iow (in) iowr (in) inactive/act (1) int0 (out) ireq (out) ts ts int1 4 (out) ts ts reset drv (in) reset (in) act iocs16 (out) iois16 (out) od/ts ts bale (in) inactive iochrdy (out) wait (out) od/2s ts sbhe (in) event (out) 2s inactive/ts aen (in) inactive/act (1) memr (in) inactive memw (in) inactive note: 1. for hardware powerdown using smout , these pins will be inactive. for software powerdown, these pins remain active. local memory interface pin name muxed pin p-down pin name type state maddr0 3 (out) faddr14 17 (out) 2s ts maddr4 (out) foe (out) 2s ts maddr5 8 (out) fl/iadata4 7 (in) ts ts mdata0 (i/o) eeprom1sk(out) ts ts mdata1 (i/o) eeprom1do(in) ts ts mdata2 (i/o) eeprom1di(out) ts ts mdata3 (i/o) ts ts we (out) fwe (out) 2s ts ras (out) 2s pu cas (out) faddr18 (out) 2s pu bootcs (out) 2s pu iapromcs (out) sa11 (in) (dual) 2s pu eepromcs (i/o) ts pd faddr19 (out) ts ts miscellaneous control muxed pin p-down dual pin name pin type state pin name name dirl (out) 2s pu dirh (out) 2s pu j0(in) act eeprom2d0 (in) j1 (i/o) ts ts eeprom2di (out) j2 (i/o) ts ts eeprom2sk (out) smout (i/o) ts act/ts pcmcia/isa (in) act jtag control pin name muxed pin p-down pin name type state tms (in) in act tck (in) in act tdi (in) in act tdo (out) 2s serial interface pin name muxed pin p-down pin name type state trmt (out) ana ts trmt (out) ana ts rcv (in) ana in act rcv (in) ana in act clsn (in) ana in act clsn (in) ana in act tdh (out) ana ts tdl (out) ana ts tdh (out) ana ts tdl (out) ana ts rd (in) ana in act rd (in) ana in act x1 (in) in act x2 (out) 2s ts liled (out) 2s ts poled (out) 2s ts actled (out) 2s ts auiled (out) bnc dis (out) 2s ts legend: tsetristate. odeopen drain. 2setwo state, will be found in eithe ra1or0 logic level. anaeanalog pin (all serial interface signals). acteinput buffer is active during power down. in acteinput buffer is inactive during power down. pueoutput in inactive state with weak internal pull-up during power down. pdeoutput in inactive state with weak internal pull-down during power down. dualedual function pin. 14
82595TX 3.0 82595TX internal architecture overview figure 1 shows a high level block diagram of the 82595TX. the 82595TX is divided into four main subsections; a system interface, a local memory sub-system interface, a csma/cd unit, and a serial interface. 3.1 system interface overview the 82595TX's system interface subsection in- cludes a glueless isa or pcmcia bus interface (se- lectable by strapping), and the 82595TX's io regis- ters (including the 82595TX's command, status, and data in/out registers). the system interface block also interfaces with the 82595TX's local memory in- terface subsystem and csma/cd subsystem. the bus interface logic provides the control, ad- dress, and data interface to either an isa compatible or pcmcia revision 2.0 bus. the 82595TX decodes up to 1m of total memory address space. address decoding within 16k block increments (a14 a19) are used for flash or boot eprom. io accesses are decoded throughout the 1 kbyte pc io address range (a10 and a11 provide up to 4k of io address- ing and are used for plug n' play). the 82595TX data bus interface provides either an 8- or 16-bit in- terface to the host system's data bus. the control interface provides complete handshaking interface with the system bus to enable transfer of data be- tween the 82595TX solution and the host system. this logic also controls the direction of the data bus transceivers. the 82595TX's io registers provide 3 banks of di- rectly addressable registers which are used as the control and data interface to the 82595TX. there are 16 io registers per bank, with only one bank enabled at a time. this allows the complete 82595TX software interface to be contained in one 16-byte io space. the base address of this io space is selectable via either software (which can be stored in a serial eeprom interfaced to either of two ports in the 82595TX), or by strapping the 82595TX io jumper block (j0 j2). the 82595TX can also detect conflicts to its base io space, and automatically resolve these conflicts either by allow- ing the selection of one plug n' play card from multi- ple cards (using plug n' play software), or by map- ping itself into an un-used io space (automatic io resolution). included in the 82595TX io registers are the command register, the status register, and the local memory io port register, which provides the data interface to the local dram buffer con- tained in an 82595TX solution. functions such as io window mapping, interrupt enable, rcv and xmt buffer initialization, etc. are also configured and con- trolled through the io registers. 3.1.1 concurrent processing functionality the 82595TX's concurrent processing feature sig- nificantly enchances data throughput performance by performing both system bus and serial link activi- ties concurrently. transmission of a frame is started by the 82595TX before that frame is completely cop- ied into local memory. during reception, a frame is processed by the host cpu before that frame is en- tirely copied to local memory. transmit concurrent processing feature is enabled by writing to bank 2, register 1, bit 0 . a 1 written to this bit enables this functionality, a 0 (default) disables it. to enable re- ceive concurrent processing, bank 1, register 7 must be programmed to value other than 00h (00h disables rcv concurrent processing, and is de- fault). (see section 4.1 for the format of io bank 1 and 2.) concurrent processing is not recommended for 8-bit interfaces. for more information on trans- mit and receive concurrent processing, refer to section 7.0 and section 8.0. 3.2 local memory interface the 82595TX's local memory interface includes a dma unit which controls data transfers to or from the 82595TX's local dram, control for access to an ia prom and a boot eprom/flash, and two in- terfaces to a serial eeprom. the local memory in- terface subsection also arbitrates accesses to the local memory by the host cpu and the 82595TX. data transfers between the 82595TX and the local dram are always through the 82595TX's local memory 16-bit/32-bit io port. this allows the entire dram memory (up to 64 kbytes) to be mapped into one io location in the host systems io map. by setting a configuration bit in the 82595TX's io registers (32io/har y ), the local memory can be extended from 16 bits to a full 32 bits. during 32-bit accesses, the cpu would perform a doubleword ac- cess addressed to register 12 of bank0. the isa bus will break this access up into two 16-bit access- es to registers 12/13 followed by registers 14/15, (or 4 sequential 8-bit accesses in an 8-bit interface). the cpu always accesses the 82595TX io port for receive or transmit data transfers, while the 82595TX automatically increments the address to the dram after each cpu access. the drams data path is a 4-bit interface (typically 64k by 4-bits wide, or 256k by 4-bits wide) to allow for the lowest possi- ble solution cost. the 82595TX implements a pre- fetch mechanism to the local dram so that the data is always available to the cpu as either an 8- or 16- bit word. in the case of the cpu reading from the dram, the 82595 tx reads the next four 4-bit nib- bles from the dram, the 82595TX between cpu cycles so that the data is always available as a word in the 82595TX's local memory io port register. in the case of the cpu writing to the dram, the data is 15
82595TX written into the 82595TX's local memory io port then transferred to the dram by the 82595TX be- tween cpu cycles. this prefetch mechanism of the 82595TX allows for io read and writes to the local memory to be performed with no additional wait- states (3 clocks per data transfer cycle). the dma unit provides addressing and control to move rcv or xmt data between the 82595TX and the local dram. for transmission, the cpu is re- quired only to copy the data to the local memory, initialize the 82595TX's dma current address reg- ister (car) to point to the beginning of the frame, and issue a transmit command to the 82595TX. the dma unit facilitates the transfers from the local memory to the 82595TX as transmission takes place. the dma unit will reset upon collision during a transmission, enabling automatic re-transmission of the transmit frame. during reception, the dma unit implements a recyclable ring buffer structure which can receive continuous back to back frames without cpu intervention on a per frame basis (see section 8.2 for details). the 82595TX provides address decoding and con- trol to allow access to an external boot eprom/ flash or an ia prom if these components are uti- lized in an 82595TX design (an ia prom cannot be used for plug n' play). the 82595TX also provides two complete interfaces to a serial eeprom (port1 or port2) to replace jumper blocks used to contain configuration information. port1 is used to store con- figuration information such as io mapping window, interrupt line selection, etc., and is backwards pin compatible to the 82595TX eeprom interface. port2 is used to store configuration information as in port1; in addition, it is used to store plug n' play information as defined in the plug n' play specifica- tion. the 82595TX arbitrates accesses to the local mem- ory sub-system by the cpu and the 82595TX. the arbitration unit will hold off an 82595TX dma cycle to the local memory if a cpu cycle is already in prog- ress. likewise, it will hold off the cpu if an 82595TX cycle is already in progress. the cycle which is held off will be completed on termination of the preceding cycle. 3.3 csma/cd unit the csma/cd unit implements the ieee 802.3 csma/cd protocol. it performs such functions as transmission deferral to link traffic, interframe spac- ing, exponential backoff for collision handling, ad- dress recognition, etc. the csma/cd unit serves as the interface between the local memory and the se- rial interface. it serializes data transferred from the local memory before it is passed to the serial inter- face unit for transmission. during frame reception, it converts the serial data received from the serial in- terface to a byte format before it is transferred to local memory. the csma/cd unit strips framing pa- rameters such as the preamble and sfd fields be- fore the frame is passes to memory for reception. for transmission, the csma/cd unit builds the frame format before the frame is passed to the serial interface for transmission. 3.4 serial interface the 82595TX's serial interface provides either an aui port interface or a twisted pair ethernet (tpe) interface. the aui port can be connected to an ethernet transceiver cable drop to provide a fully compliant ieee 802.3 aui interface. the aui port can also interface to a transceiver device to provide a fully compliant ieee 802.3 10base2 (cheapernet) interface. the tpe port provides a ful- ly compliant 10base-t interface. the 82595TX au- tomatically enables either to the aui or tpe inter- face depending on which medium is connected to the chip. software configuration can override this automatic selection. 4.0 accessing the 82595TX all access to the 82595TX is made through one of three banks of io registers. each bank contains 16 registers. each register in a bank is directly accessi- ble via addressing. through the use of bank switch- ing, the 82595TX utilizes only 16 io locations in the host system's io map to access each of its regis- ters. the different banks are accessed by setting the pointer field in the 82595TX command register to select each bank. the command register is reg- ister for each bank. 4.1 82595TX register map the 82595TX registers are contained in three banks of 16 io registers per bank. these three banks are shown in the following three pages. 16
82595TX 4.1.1 io bank 0 the format for io bank 0 is shown below. 76543210 reg 0 pointer abort command op code (cmd reg) rcv exec exec tx rx rx stp states states int int int int reg 1 id register 0 0 (counter) 1 (auto en) 0 1 reserved reg 2 0 0 cur/ 32 io/ exec tx rx rx stp resvrd resvrd base har mask mask mask mask reg 3 rcv car/bar (low) reg 4 rcv car/bar (high) reg 5 rcv stop reg (low) reg 6 rcv stop reg (high) reg 7 rcv copy threshold reg reg 8 00000000 (reserved) reg 9 xmt car/bar (low) reg 10 xmt car/bar (high) reg 11 host address reg/32-bit i/o (byte 0) (low) reg 12 host address reg/32-bit i/o (byte 1) (high) reg 13 local memory/32-bit i/o (byte 2) io port (low) reg 14 local memory/32-bit i/o (byte 3) io port (high) reg 15 17
82595TX 4.1.2 io bank 1 the format for io bank 1 is shown below. 76543210 reg 0 pointer abort command op code (cmd reg) tri-st alt0000 host 0 int rdy tm resvrd resvrd resvrd resvrd bus wd resvrd reg 1 fl/bt boot eprom/flash 0 int select detect decode window resvrd reg 2 0 0 i/o mapping window reg 3 00000000 (reserved) reg 4 00000000 (reserved) reg 5 00000000 (reserved) reg 6 rcv bof threshold reg reg 7 rcv lower limit reg (high byte) reg 8 rcv upper limit reg (high byte) reg 9 xmt lower limit reg (high byte) reg 10 xmt upper limit reg (high byte) reg 11 flash page flash write flash page select high enable select reg 12 00000 smout al rdy al rdy out en test pas/fl reg 13 00000000 (reserved) reg 14 00000000 (reserved) reg 15 18
82595TX 4.1.3 io bank 2 the format for io bank 2 is shown below. 76543210 reg 0 pointer abort command op code (cmd reg) disc tx chn tx chn pcmcia/ 0 0 0 tx con bad fr erstp int md isa proc en reg 1 loopback multi no sa length rx crc bc prmsc ia ins enable inmem dis mode reg 2 test1 test2 bnc/ aport jabber tpe/ pol lnk in tpe disabl aui corr dis reg 3 individual address register 0 reg 4 individual address register 1 reg 5 individual address register 2 reg 6 individual address register 3 reg 7 individual address register 4 reg 8 individual address register 5 reg 9 stepping trnoff eedo eedi eecs eesk enable reg 10 rcv no resource counter reg 11 iaprom io port reg 12 00000000 (reserved) reg 13 00000000 (reserved) reg 14 00000000 (reserved) reg 15 4.2 writing to the 82595TX writing to the 82595TX is accomplished by an io write instruction (such as an out instruction) from the host processor to one of the 82595TX registers. the 82595TX registers reside in a block of 16 con- tiguous addresses contained within the pc io ad- dress space. the mapping of this address block is programmable throughout the 1 kbyte pc io ad- dress map. the 82595TX registers are contained within three banks of io registers. when writing to a particular register, the processor must first select the correct bank (bank 0, 1 or 2) in which the register resides. once a bank is selected, all register accesses are made in that bank until a switch to another bank is performed. switching banks is accomplished by writ- ing to the ptr field of reg 0 in any bank. reg 0 is the command register of the 82595TX and its func- tionality is identical in each bank. once in the appro- 19
82595TX priate bank, the processor can write directly to any of the 82595TX registers by simply issuing an out instruction to the io address of the register. 4.3 reading from the 82595TX reading from the 82595TX is accomplished by an io read instruction (such as an in instruction) from the host processor to one of the 82595TX registers. when reading from a particular register, the proces- sor must first select the correct bank (bank 0, 1 or 2) in which the register resides. once in the appropri- ate bank, the processor can read directly from any of the 82595TX registers by simply issuing an in in- struction to the io address of the register. 4.4 local dram accesses io mapping the local dram memory of an 82595TX solution allows it to appear as simply an io port to the host system. this allows an 82595TX solution to work in pcs which do not have enough space in their system memory map to accommodate the ad- dition of lan buffer memory (typically 16 kbytes to 64 kbytes) into the map. the entire local memory (up to 64 kbytes) is mapped into one 16-bit io port location. for all io-mapped accesses to the local memory of a 82595TX solution, the 82595TX per- forms the io address decoding and the isa bus in- terface handshake and asserts the address and control signals to the local memory. 4.4.1 writing to local memory the local memory of an 82595TX solution is written to whenever the host cpu performs a write opera- tion to the 82595TX local memory io port. prior to writing a block of data to the local memory, the cpu should update the 82595TX host address register with the first address to be written. the cpu then copies the data to the local memory by writing it to the 82595TX local memory io port. the addressing to the local memory is provided by the host address register which is automatically incremented by the 82595TX upon completion of each write cycle. this allows sequential accesses to the local memory, even though the io port address accessed does not change. 4.4.2 reading from local memory the local memory of an 82595TX solution is read from whenever the host cpu performs a read oper- ation from the 82595TX local memory io port. prior to reading a block of data from the local memory, the cpu should utilize the 82595TX host address register to point to first address to be read. the cpu then reads the data from the local memory through the 82595TX local memory io port. the addressing to the local memory is provided by the host address register which is automatically incre- mented by the 82595TX upon completion of each read cycle. 20
82595TX 4.5 serial eeprom interface a serial eeprom, a hyundai hy93c46 or equiva- lent ic, stores configuration data for the 82595TX. the use of an eeprom enables 82595TX designs to be implemented without jumpers (the use of jump- ers to select io windows is optional.) the 85295tx provides two complete interfaces to a serial eeprom (port1 or port2, and only one port can be used). port1 is used to store configuration informa- tion in the eeprom, such as io base address and interrupt selection, and is backwards pin compatible to the 82595 eeprom interface. port2 stores con- figuration information as in port1; in addition, it is used to store plug n' play information as defined in the plug n' play specification. plug n' play allows peripheral functions to be added to a pc (such as adapter cards) without the need to individually con- figure each parameter (e.g. interrupt, io ad- dress, etc). information describing system resources are contained within the 82595TX configuration reg- isters. this allows auto-configuration software, which is usually contained in the bios or o/s, to identify system resource usage, identify conflicts and automatically re-configure the 82595TX. the 82595TX automatically accesses register 0 of the eeprom upon a reset in isa bus interface mode. register 0 contains the information that the 82595TX must be configured to allow cpu accesses to it (io mapping window, flash detect enable, auto i/o enable, boot eprom/flash window, host bus width, and plug n' play enable) following a system boot. the format for eeprom register 0 is shown in figure 4-1. note that all 0's are assumed to be reserved. in the case where an eeprom is either unprogrammed (each bit defaults to a 1) or completely erased (all 0's), the 82595TX will default to io address 300h. for additional information regarding a plug n' play implementation for the 82595TX, please consult the 82595TX user manual and lan595tx specification, available through your local sales representative. the latest plug n' play specification is available by microsoft. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 io mapping window 0 flash 0 auto bt/flsh window hst 0 pnp msb lsb det i/o en msb lsb wdt en figure 4-1. eeprom register 0 21
82595TX 4.6 boot eprom/flash interface the boot eprom/flash of an 82595TX solution is read from or written to (flash only) whenever the host cpu performs a read or a write operation to a memory location that is within the boot eprom/ flash mapping window. this window is program- mable throughout the isa prom address range (c8000 dffff) by configuring the 82595TX boot eprom decode window register (bank 1, register 2, bits 4 6). the 82595TX asserts the bootcs y signal when it decodes a valid access. up to 1 mbytes of flash can be addressed by the 82595TX. 4.7 ia prom interface the 82595TX supports an ia prom interface. im- plementation of an ia prom in a 82595TX solution is optional. the ia can also be stored in the serial eeprom. in this case the ia prom is not needed. for plug n' play, an ia prom cannot be used. 4.8 pcmcia cis structures the 82595TX supports access to 1k of attribute memory when configured for pcmcia support. attri- bute memory is defined by the pcmcia standard to be comprised of the card information structure (flash memory referred to as cis residing at mem- ory offset 0 to 1015:decimal) and 4 8-bit card con- figuration registers which reside at memory offset 1016 to 1022 on even boundaries only (1016, 1018, 1020, 1022). these four registers are contained in the 82595TX. they are memory mapped and are ac- cessed when ce1 and reg are asserted low along with the decode of a0 a9 and assertion of either a oe or we . the 82595TX card configuration regis- ters are shown at the bottom of this page. 4.9 pcmcia decode functions the attribute memory and common memory map for a pcmcia card is shown below. attribute memo- ry is defined as the cis structures (residing in flash below 1k) and the ccr registers (residing in the 82595TX). common memory is defined as the flash memory above 1k. 128 kbyte flash 70 common memory flash 131,071 1025 1024 * ccr 3 (82595TX) 1022 access to 82595TX locations for these ccr 2 (82595TX) 1020 ccr 1 (82595TX) 1018 ccr 0 (82595TX) 1016 registers flash cis 1015 01 00 82595TX card configuration registers 76543210 reset 00000xipenioenccr0 (addr 1016) 0 0 iois8 evntwk 0 0 ireq 0 ccr 1 (addr 1018) 00000000ccr2 (addr 1020) 00000000ccr3 (addr 1022) note: all 0's in the above registers are reserved. 22
82595TX 5.0 command and status interface the format for the 82595TX command register is shown in figure 5-1. the command register resides in register 0 of each of the three io banks of the 82595TX, and can be accessed in any of these banks. the command register is accessed by writ- ing to or reading from the io address for register 0. 5.1 command op code field bits 0 through 4 of the command register comprise the command op code field. a command is issued to the 82595TX by writing it into the command op code field. a command can be issued to the 82595TX at any time; however in certain cases the command may be ignored (for example, issuing a transmit command while a transmit is already in progress). in these cases the command is not per- formed, and no interrupt will result from it. the command op code field can also be read. in this case it will indicate an execution status event other than transmit done (tdr done, diag- nose done, mc-setup done, dump done, init done, and power-up) has been completed. this field is valid only when the exec int bit (bank 0, reg 1, bit 3) is set. 5.2 abort (bit 5) this bit indicates if an execution command other than transmit was aborted while in progress. this bit provides status information only. it should be writ- ten to a 0 whenever the command register is writ- ten to. 5.3 pointer field (bits 6 and 7) the pointer field controls which 82595TX io register bank is currently to be accessed (bank 0, bank 1, or bank 2). writing a 00:b to the pointer field selects bank 0, 01:b for bank 1, and 10:b for bank 2. the pointer field is valid only when the switch bank (0h) command is issued. this field will be ignored for any other command. the 82595TX will continue to operate in a current bank until a different bank is selected. upon power up of the device or reset, the 82595TX will default to bank 0. 76543210 pointer abort command op code reg 0 (cmd reg) figure 5-1. 82595TX command register 281630 3 figure 5-2. 82595TX command interface 23
82595TX 5.4 82595TX status interface the status of the 82595TX can be read from regis- ter 1 of bank 0, with additional status information contained in register 0 (the command register). figure 5-3 shows these registers. other information concerning the configuration and initialization of the 82595TX and its registers can be obtained by direct- ly reading the 82595TX registers. when read, the command op code field indicates which event (mc done, init done, tdr done, or diag done) has been completed. this field is valid only when the exec int bit (bank 0, reg 1, bit 3) is set to a 1. reading the pointer field indicates which bank the 82595TX is currently operating in. register 1 in bank 0 contains the 82595TX interrupts status as well as the current states of the rcv and execu- tion units of the 82595TX. resultant status from events such as the completion of a transmission or the reception of an incoming frame is contained in the status field of the memory structures for these particular events. 6.0 initialization upon either a software or hardware reset, the 82595TX enters into its initialization sequence. when the 82595TX is interfaced to an isa bus, the 82595TX reads information from its eeprom and jumper block (if utilized) which configures critical pa- rameters (io address mapping, etc.) to allow initial accesses to the 82595TX during the host system's initialization sequence and also access by the soft- ware device driver. the 82595TX can also be config- ured (via the eeprom) to automatically resolve any conflicts to its io address location either by moving its io address offset to an unused location in the case that a conflict occurs, or by using the plug n' play software to the i/o address location. this pro- cess eliminates a large majority of lan end-user setup problems. the 82595TX can be configured to operate with isa systems that require early deassertion of the iochrdy signal to its low (not ready) state. the 82595TX, along with its software driver, can perform a test at initialization to determine if early iochrdy deassertion is required. the 82595TX, when interfaced to a pcmcia bus, simply powers up with default pcmcia configuration values enabled. this is the only step for pcmcia initialization, since the pcmcia bus requires no se- lection of interrupts, io space, etc. 76543210 pointer abort execution event reg 0 (cmd reg) rcv exec exec tx rx rx stp states states int int int int reg 1 (bank 0) figure 5-3. 82595TX status information 24
82595TX 7.0 frame transmission the 82595TX performs all of the necessary func- tions needed to transmit frames from its local mem- ory. if transmit concurrent processing is enabled, the cpu must only program the base and host ad- dress register with the starting address to be trans- mitted, copy a portion of the frame into the 82595TX's transmit buffer located in local memory (the number of bytes for this first portion is deter- mined by the software driver without causing an un- derrun), issue a xmt command to the 82595TX, and complete the data copies for this frame to local memory. if transmit concurrent processing is dis- abled, the cpu must copy an entire frame into the 82595TX's transmit buffer located in local memory, set up the 82595TX's current address registers to point to that frame, and issue a xmt command to the 82559tx. the 82595TX performs all the link management functions, dma operations, and statis- tics keeping to handle transmission onto the link and communicate the status of the transmission to the cpu. the 82595TX performs automatic retransmis- sion on collision with no cpu interaction. 7.1 82595TX xmt block memory format the format in which a xmt block is written to memo- ry by the cpu is shown in figure 7-1 for a 16-bit interface. figure 7-2 shows this structure for an 8-bit interface. 281630 4 figure 7-1. xmt block memory structure (16-bit) 25
82595TX 281630 5 figure 7-2. xmt block memory structure (8-bit) 26
82595TX status field the two bytes of the status field (status 0 and status 1) are shown in detail in figure 7-3. in a 16-bit wide interface, these two bytes will combine to form one word. this field is originally set to all 0's by the cpu as the xmt block is copied to memory. it is updated by the 82595TX upon completion of the transmission. 7.2 xmt chaining the 82595TX can transmit consecutive frames with- out the cpu having issued a separate transmit command for each frame. this is called transmit chaining. the 82595TX transmit chaining memory structure for a 16-bit interface is shown in figure 7-4, with an 8-bit interface shown in figure 7-5. the 82595TX registers which control the memory struc- ture are also shown. the cpu places multiple xmt blocks in the transmit buffer. the 82595TX will transmit each frame in the chain, reporting the status for each frame in its status field. if concurrent processing is enabled, the copy of additional frames in a chain will take place while the first portion of the chain (one or more frames) is being transmitted by the 82595TX. this chain can be dynamically updat- ed by the cpu to add more frames to the chain. the transmit chain can be configured to terminate upon an errored frame (maximum collisions, underrun, lost crs, etc.) or it can continue to the next frame in the chain. the 82595TX can be configured to interrupt upon completion of each transmission or to interrupt at the end of the transmit chain only (it always inter- rupts upon an errored condition). 76 5 4321 0 tx def hrt bet max col x no of collisions status 0 coll x tx ok 0 ltcol lst crs x und run status 1 figure 7-3. transmit result 27
82595TX 281630 6 figure 7-4. 82595TX xmt chaining memory structure 28
82595TX 281630 7 figure 7-5. xmt block memory structure (8-bit) 29
82595TX 7.3 automatic retransmission on collision the 82595TX performs automatic retransmission when a collision is experienced within the first slot time of the transmission with no intervention by the cpu. the 82595TX performs jamming, exponential backoff, and retransmission attempts as specified by the ieee 802.3 spec. the 82595TX reaccesses its local memory automatically on collision. this allows the 82595TX to retransmit up to 15 times after the initial collision with no cpu interaction. the 82595TX reaccesses the data in its transmit buffer by simply resetting the value of its current address register back to the value of the base ad- dress register (the beginning of the xmt block) and repeating the dma process to access the data in the transmit buffer again. once it regains access to the link, retransmission is attempted. when transmit chaining is utilized, the process for retransmission is exactly the same. only the current frame in the chain will be retransmitted, since the base address register is updated upon transmission of each frame. 8.0 frame reception the 82595TX implements a recyclable ring buffer dma structure to support the reception of back to back incoming rcv frames with minimal cpu over- head. the structure of the rcv frames in memory is optimized to allow the cpu to process each frame with as few software processing steps as pos- sible. the frame format is arranged so that all of the required infomation for each frame (status, size, etc.) is located at the beginning of the frame. 8.1 82595TX rcv memory structure the 82595TX rcv memory structure for a 16-bit in- terface is shown in figure 8-1. figure 8-2 shows this structure for the 8-bit interface. once an incoming frame passes the 82595TX's address filtering, the 82595TX deposits the frame into the rcv data field of the rcv memory structure. the fields which pre- cede the rcv data field, event, status, byte count, next frame pointer, and the event field of the fol- lowing frame, are updated upon the end of the frame after all of the incoming data has been deposited in the rcv data field. if receive concurrent process- ing is enabled, the cpu processes the receive frame without the entire frame being deposited by the 82595TX to the rcv data field. the 85295tx, along with the software driver, determines the por- tion of the frame being copied to host memory be- fore the rest of that frame is copied to local memory. an interrrupt is asserted by the 82595TX (eof) after frame reception has been completed. if the 82595TX is configured to discard bad frames, it will discard all incoming errored frames by reset- ting its dma current address register back to the value of the base address register and not updat- ing any of the fields in the rcv frame structure. this area will now be reused to store the next incoming frame. 30
82595TX 281630 8 figure 8-1. 82595TX rcv memory structure (16-bit) 31
82595TX 281630 9 figure 8-2. 82595TX rcv memory structure (8-bit) 32
82595TX status field the two bytes of the status field (status 0 and status 1) are shown in detail in figure 8-3. in a 16-bit wide interface, these two bytes will combine to form one word. the 82595TX provides this field for each incoming frame. 8.2 rcv ring buffer operation the 82595TX rcv ring buffer operation is illustrat- ed in figure 8-4. the 82595TX copies received frames sequentially into the rcv buffer area of the local memory. the cpu processes these frames by copying the frames from the local memory. after a frame is processed, the cpu updates the 82595TX's stop register to point to the last location processed. this indicates that the rcv buffer memory which precedes the value programmed in the stop regis- ter is now free area (it has been processed by the cpu). when the 82595TX reaches the end of the rcv buffer (the upper limit register value) it will now wrap around back to the beginning of the buff- er, and continue to copy rcv frames into the buffer, beginning at the value pointed to by the lower limit register. the 82595TX will continue to copy frames into the rcv buffer area as long as it does not reach the address pointed to by the stop register (if this does occur, the 82595TX stops copying the frames into memory and issues an interrupt to the cpu). as the cpu processes additional incoming frames, the stop register value continues to be moved. this ac- tion allows the cpu to keep ahead of the incoming frames and allows the ring buffer to be continually recycled as the memory space consumed by an in- coming frame is reused as that frame is processed. 7654 3 210 srt frm x x 1 x x ia mch rcld status 0 typ/len 0 rcv ok len err crc err alg err 0 ovr rn status 1 figure 8-3. rcv status field 281630 10 figure 8-4. 82595TX rcv ring buffer operation 33
82595TX 9.0 serial interface the 82595TX's serial interface subsystem incorpo- rates all the active circuitry required to interface the 82595TX to 10base-t networks or to the attach- ment unit (aui) interface. it includes on-chip aui and tpe drivers and receivers as well as manchester encoder/decoder and clock recovery circuitry. the aui port can be connected to an ethernet trans- ceiver cable drop to provide a fully compliant ieee 802.3 aui interface. the aui port can also be inter- faced to a transceiver to provide a fully compliant ieee 802.3 10base2 (cheapernet) interface. the tpe port provides a fully compliant 10base-t inter- face. the 82595TX automatically enables either the aui or tpe interface, depending on which medium is active. this automatic selection can be overridden by software configuration. the tpe interface also features a polarity fault detection and correction cir- cuit which will detect and correct a polarity error on the twisted pair wire, the most common wiring fault in twisted pair networks. a 20 mhz parallel resonant crystal is used to control the clock generation oscillator, which provides the basic 20 mhz clock source. an internal divide-by- two counter generates the 10 mhz g 0.01% clock required by the ieee 802.3 specification. we recommend that a crystal that meets the follow- ing specifications be used: # quartz crystal # 20.00 mhz g 0.002% at 25 c # accuracy g 0.005% over full operating temper- ature, 0 cto a 70 c # parallel resonant with 20 pf load fundamental mode several vendors have such crystals; either off-the- shelf or custom-made. two possible vendors are: 1. m-tron industries, inc. yankton, sd 57078 specifications: part no. hc49 with 20 mhz, 50 ppm over 0 cto a 70 c, and 20 pf fundamental load. 2. crystek corporation 100 crystal drive ft. myers, fl 33907 part no. 013212 the accuracy of the crystal oscillator frequency de- pends on the pc board characteristics; therefore, it is advisable to keep the x1 and x2 traces as short as possible. the optimum value of c1 and c2 should be determined experimentally under nominal operat- ing conditions. the typical value of c1 and c2 is between 22 pf and 35 pf. an external 20 mhz mos-level clock may be applied to pin x1, if pin x2 is left floating. a summary of the 82595TX's serial interface subsections functions is shown below: # manchester encoder/decoder and clock recovery # diagnostic loopback # reset-low-power mode # network status indicators # defeatable jabber timer # user test modes # complies with ieee 802.3 aui standard e direct interface to aui transformers e on-chip aui squelch # complies with ieee 802.3 10base-t for twisted pair ethernet e selectable polarity detection and correction e direct interface to tpe analog filters e on-chip tpe squelch e defeatable link integrity for pre-standard networks e supports 4 leds (link integrity, activity, aui/bnc dis and polarity correction) 34
82595TX 10.0 application notes this section is intended to provide ethernet lan de- signers with a basic understanding of how the 82595TX is used in a buffered lan design. 10.1 bus interface the 82595TX bus interface unit integrates the inter- face to both an isa compatible bus and a pcmcia rev 2.0 bus. selection of the desired bus interface is done by strapping the pcmcia/isa pin accordingly. two 74als245 transceivers are used to buffer the 82595TX's data bus, with the 82595TX providing the control over the transceivers. the data bus is not buffered in a pcmcia design. the 82595TX also provides the complete control and address interface to the host system bus. when the isa bus interface is selected, it implements the complete isa bus pro- tocol. when pcmcia interface is selected, the com- plete pcmcia bus interface protocol is implement- ed. 10.2 local memory interface the 82595TX's local memory interface includes a dma unit which controls data transfers between the 82595TX and the local memory dram. the 82595TX can support up to 64 kbytes of local dram. the 82595TX provides address decoding and con- trol to allow access to an external boot eprom or a flash. addition of a boot eprom or flash to an isa solution is optional. the flash is always con- tained as part of a pcmcia solution. the 82595TX also supports a separate ia prom if one is desired. for this example, the ia is assumed to be stored in the serial eeprom for the isa solution and in the flash for the pcmcia solution. 10.3 eeprom interface (isa only) the 82595TX provides a complete interface to a se- rial eeprom for isa adapter designs. for isa moth- erboard designs and pcmcia designs, the eeprom is not required. the eeprom is used to store configuration information such as memory and io mapping window, interrupt line selection, plug n' play resource data local bus width, etc. the eeprom is used to replace jumper blocks which previously contained this type of information. the 82595TX also contains an optional jumper interface (j0 j2). these jumpers can be used to select the io mapping window of the solution. in the case of this design, the jumper block is grounded (disabled) with the io mapping window being contained in the eeprom. 10.4 serial interface the 82595TX's serial interface provides either an aui port interface or a twisted pair ethernet (tpe) interface. the aui port can be connected to an ethernet transceiver cable drop to provide a fully compliant ieee 802.3 10base5 interface. the aui port can also be interfaced to a transceiver device on the adapter to provide a fully compliant ieee 802.3 10base2 (cheapernet) interface. the tpe port provides a fully compliant 10base-t interface. the 82595TX automatically enables either the aui or tpe interface, depending on which medium is connected to the chip. this automatic selection can be overridden by software configuration. 10.4.1 aui circuit when used in conjunction with pulse transformers, the 82595TX provides a complete ieee 802.3 aui interface. in order to meet the 16v fault tolerance specification of ieee 802.3, a pulse transformer is recommended. the transformer should be placed between the trmt, rcv, and clsn pairs of the 82595TX and the do, di, and ci pairs of the aui (db-15) connector. the pulse transformer should have the following characteristics: # 75 m h minimum inductance (100 m h recom- mended) # 2000v isolation between the primary and second- ary windings # 2000v isolation between the primaries of sepa- rate transformers # 1:1 turns ratio the rcv and clsn input pairs should each be ter- minated by 78.7 x g 1% resistors. 10.4.2 tpe circuit the 82595TX provides the line drivers and receivers needed to directly interface to the tpe analog filter network. the tpe receive section requires a 100 x termination resistor, a filter section (filter, isolation transformer, and a common mode choke) as de- scribed by the 10base-t 802.3i-1990 specification. the tpe transmit section is implemented by con- necting the 82595TX's four tpe outputs (tdh, tdh , tdl, tdl ) to a resistor summing network to form the differential output signal. the parallel resistance of r5 and r6 sets the transmitters maximum output voltage, while the difference (r5 b r6)/r5 a r6), is used to reduce the amplitude of the second half of the fat bit (100 ns) to a predetermined level. this predistortion reduces line overcharging, a major source of jitter in the tpe environment. the output of the summing network is then fed into the above 35
82595TX mentioned filter and then to the 10base-t connec- tor (rj-45). analog front end solutions can be pur- chased in a single-chip solution from several manu- facturers. the solution described in this data sheet uses the pulse engineering (pe65434) afe. 10.4.3 led circuit the 82595TX's internal led drivers support four led indicators displaying node status and activity (i.e., transmit data, receive data, collisions, link in- tegrity, polarity correction, and port (tpe/aui). to implement the led indicators, connect the led driv- er output to an led in series with a 510 x resistor tied to v cc . each driver can sink up to 10 ma of current with an output impedance of less than 50 x . 10.5 layout guidelines 10.5.1 general the analog section, as well as the entire board itself, should conform to good high-frequency practices and standards to minimize switching transients and parasitic interaction between various circuits. to achieve this, follow these guidelines: make power supply and ground traces as thick as possible. this will reduce high-frequency cross cou- pling caused by the inductance of thin traces. connect logic and chassis ground together. you must connect all v cc pins to the same power supply and all v ss pins to the same ground plane. use separate decoupling and noise conditions per power-supply/ground pin. close signal paths to ground as close as possible to their sources to avoid ground loops and noise cross coupling. use high-loss magnetic beads on power supply dis- tribution lines. 10.5.2 crystal the crystal should be adjacent to the 82595TX and trace lengths should be as short as possible. the x1 and x2 traces should be symmetrical. 10.5.3 82595TX analog differential signals the differential signals from the 82595TX to the transformers, analog front end, and the connectors should be symmetrical for each pair and as short as possible. as a general rule, the trace widths should be one to three times the distance between the pcb layers to eliminate excessive trace inductance. the differential signals should also be isolated from the high speed logic signals on the same layer as well as on any sublayers of the pcb. group each of the circuits together, but keep them separate from each other. separate their grounds. in layout, the circuitry from the connectors to the filter network should have the ground and power planes removed from beneath it. this will prevent ground noise from being induced into the analog front end. all trace bends should not exceed 45 degrees. 10.5.4 decoupling considerations four 0.1 m f ceramic capacitors should be used. place one on each side in the center of the i.c. (v cc pins 23, 51, 89, 125 are recommended) adjacent to the 82595TX. connect the capacitors directly to the v cc pins on the 82595TX and then directly to the ground plane. in addition to the 0.1 m f capacitors, a 10 m f tantalum should be used near one of the 82595TX's v cc pins. the proximity of this capacitor to the 82595TX is not as critical as in the case of the 0.1 m f capacitors. placement of this capacitor within approximately one inch of the 82595TX is recom- mended. 36
82595TX 11.0 electrical specifications and timings 11.1 absolute maximum ratings case temperature under bias 0 cto a 85 c storage temperature b 65 cto a 140 c all output and supply voltages b 0.5v to a 7v all input voltages b 1.0v to a 6.0v (1) further information on the quality and reliability of the 82595TX may be found in the components quality and reliability handbook , order number 210997. notice: this data sheet contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest data sheet be- fore finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. table 11-1. d.c. characteristics (t c e 0 cto a 85 c, v cc e 5v g 5%) symbol parameter min max units test conditions v il input low voltage (ttl) b 0.3 a 0.8 v v ih input high voltage (ttl) 2.0 v cc a 0.3 v v ih(jumpr) input high voltage (jumpers) 3.0 v cc a 0.3 v v ol1 output low voltage (11) 0.45 v i ol e 2ma v ol2 output low voltage (11) 0.45 v i ol e 6ma v ol3 output low voltage (11) 0.45 v i ol e 12 ma v ol4 output low voltage (11) 0.45 v i ol e 17 ma v oh output high voltage 2.4 v i oh eb 1ma v ol (led) (2) output low voltage 0.45 v i ol e 10 ma v oh (led) output high voltage 3.9 v i oh eb 500 m a i lp leakage current, low power mode (3) g 10 m a0 s v i s v cc r diff input differential-resistance (4) 10 k x dc v idf (tpe) (5) input differential accept g 0.5 g 3.1 v p 5 mhz s f s 10 mhz input differential reject g 0.3 v p r s (tpe) (6) output source resistance 6 13 x l i load l e 25 ma v idf (aui) (7) input differential accept g 0.3 g 1.5 v p input differential reject g 0.16 v p v icm (aui) ac input common mode g 0.5 v p f s 40 khz g 0.1 v p 40 khz s f s 10 mhz v odf (aui) (8) output differential voltage g 0.45 g 1.2 v i osc (aui) aui output short circuit current g 150 ma short circuit to v cc or gnd vu (aui) output differential undershoot b 100 mv v odi (aui) differential idle voltage (9) 40 mv i cc power supply current 90 ma i ccpd power supply current 1 ma power down mode c in (10) input capacitance 10 pf @ f e 1 mhz notes: 1. the voltage levels for rcv and clsn pairs are b 0.75v to a 8.5v. 2. led pins: actled, tpe e bnc e aui , poled, liled. 3. pins: actled, tpe e bnc e aui , poled, liled. 4. pins: rd to rd , rcv to rcv and clns to clsn . 5. tpe input pins: rd and rd . 6. tpe output pins: tdh, tdh , tdl and tdl ,r s measure v cc or v ss to pin. 7. aui input pins: rcv and clsn pairs. 8. aui output pins: tpmt pair. 9. measured 8.0 m s after last positive transition of data packet. 10. characterized, not tested. 11. v ol1 is pins sd 015 , ras , cas , eepromcs, iapromcs , bootcs , dirh , and dirl .v ol2 is pins mdata 03 , maddr 08 , tdo, lwe , sbhe , and smout .v ol3 is pins iochrdy and int 04 .v ol4 is iocs16 . 37
82595TX 11.1.1 package thermal specifications the 82595TX is specified for operation when case temperature is within the range of 0 cto85 c. the case temperature may be measured in any environ- ment to determine whether the 82595TX is within the specified operating range. the case temperature should be measured at the center of the top surface opposite the pins. the ambient temperature is guaranteed as long as t c is not violated. the ambient temperature can be calculated from the i ja and the i jc from the follow- ing equations: t j e t c a p * i jc t a e t j b p * i ja t c e t a a p * i ja b i jc i ja and i jc values for the 144 tqfp package are as follows: thermal resistance ( c/watt) i jc i ja b vs b airflow ft/min (m/sec) 0 (0) 200 (1.01) 17 48 38 11.2 a.c. timing characteristics 281630 11 figure 11-1. voltage levels for differential input timing measurements (rcv and clsn pairs) 281630 12 figure 11-2. voltage levels for tdh, tdl, tdh and tdl 281630 13 figure 11-3. voltage levels for trmt pair output timing measurements 281630 14 figure 11-4. voltage levels for differential input timing measurements (rd pair) 11.3 a.c. measurement conditions 1. t c e 0 cto a 85 c, v cc e 5v g 5% 2. the signal levels are referred to in figures 1, 2, 3 and 4. 3. a.c. loads: a) aui differential: a 10 pf total capacitance from each terminal to ground and a load resis- tor of 78 x g 1% in parallel with a 27 m h g 5% inductor between terminals. b) tpe: 20 pf total capacitance to ground. 281630 15 figure 11-5. x1 input voltage levels for timing measurements 38
82595TX table 11-2. clock timing symbol parameter min max unit t1 x1 cycle time 49.995 50.005 ns t2 x1 fall time 5 ns t3 x1 rise time 5 ns t4 x1 low time 15 ns t5 x1 high time 15 ns 11.4 isa interface timing table 11-3. isa 16-bit i/o access parameter description min max units comments t1a bale active to inactive 50 ns t2a bale active from command inactive 35 ns t3a aen valid to falling edge of bale 20 ns applies for early iochrdy t4a aen valid to i/o command active 100 ns t5a aen valid from i/o command inactive 30 ns t6a sa valid to falling bale 20 ns applies for early iochrdy t7a sa to cmd active 63 ns t8a sa valid hold from cmd inactive 42 ns t9a valid sa to iocs16 active 100 ns t10a iocs16 valid hold from valid sa 0 ns t11a cmd active to inactive 125 ns t12a cmd inactive to active 92 ns before i/o command t13a active cmd to valid iochrdy 18 ns t14a iochrdy inactive pulse 12 m s t15a cmd active hold from iochrdy active 80 ns applies to ready cycles t16a data driven from read cmd active 0 ns t17a valid read data from cmd active 54 ns applies to standard cycles only t18a valid read data from iochrdy active 42 ns applies to ready cycles only t19a read data hold from cmd inactive 0 ns t20a read cmd inactive to data tristate 30 ns t21a cmd to write data active 62 ns t22a write data hold from cmd inactive 25 ns t23a write cmd inactive to data tristate 30 ns t24a iochrdy inactive to cmd active 15 ns applies to early iochrdy t25a bale inactive to cmd active 55 ns applies to early iochrdy t26a read cmd active to dirx active 34 ns t27a read cmd inactive to dirx inactive 15 ns 39
82595TX table 11-4. isa 8-bit i/o access parameter description min max units comments t1b bale active to inactive 50 ns t2b bale active from command inactive 35 ns t3b aen valid to falling edge of bale 20 ns applies to early iochrdy t4b aen valid to i/o command active 100 ns t5b aen valid from i/o command inactive 30 ns t6b sa valid to falling bale 20 ns applies to early iochrdy t7b sa to cmd active 63 ns t8b sa valid hold from cmd inactive 42 ns t9b valid sa to iocs16 active 100 ns t10b iocs16 valid hold from valid sa 0 ns t11b cmd active to inactive 125 ns t12b cmd inactive to active 92 ns before i/o command t13b active cmd to valid iochrdy 18 ns t14b iochrdy inactive pulse 12 m s t15b cmd active hold from iochrdy active 80 ns applies to ready cycles t16b data driven from read cmd active 0 ns t17b valid read data from cmd active 54 ns applies to standard cycles only t18b valid read data from iochrdy active 42 ns applies to ready cycles only t19b read data hold from cmd inactive 0 ns t20b read cmd inactive to data tristate 30 ns t21b cmd to write data active 62 ns t22b write data hold from cmd inactive 15 ns t23b write cmd inactive to data tristate 30 ns t24b iochrdy inactive to cmd active 15 ns applies to early iochrdy t25b bale inactive to cmd active 55 ns applies to early iochrdy t26b read cmd active to dirx active 34 ns t27b read cmd inactive to dirx inactive 15 ns 40
82595TX table 11-5. isa 8-bit memory access parameter description min max units comments t1c bale active to inactive 50 ns t2c bale active from command inactive 35 ns t4c aen valid to command active 100 ns t5c aen valid from command inactive 30 ns t7c sa to cmd active 63 ns t8c sa valid hold from cmd inactive 42 ns t11c cmd active to inactive 125 ns t12c cmd inactive to active 60 ns before memory command t13c active cmd to valid iochrdy 18 ns t14c iochrdy inactive pulse 12 m s t15c cmd active hold from iochrdy active 80 ns applies to ready cycles t16c data driven from read cmd active 0 ns t18c valid read data from iochrdy active 42 ns applies to ready cycles only t19c read data hold from cmd inactive 0 ns t20c read cmd inactive to data tristate 30 ns t21c cmd to write data active 52 ns t23c write cmd inactive to data tristate 30 ns t26c read cmd active to dirx active 34 ns t27c read cmd inactive to dirx inactive 15 ns 41
82595TX 281630 16 figure 11-6. isa-compatible cycle 42
82595TX 281630 17 figure 11-7. early iochrdy cycle 43
82595TX 11.5 pcmcia interface timing table 11-6. pcmcia i/o access parameter description min max units comments t30a address valid to cmd active 70 ns t31a cmd inactive to address change 20 ns t32a address valid to iois16 active/inactive 35 ns t33a address change to iois16 change 35 ns t34a reg active before cmd active 5 ns t35a reg active after cmd inactive 0 ns t36a ce active/inactive before cmd active 5 ns t37a ce active/inactive after cmd inactive 20 ns t38a cmd active to inactive 165 ns t39a cmd active to wait active/inactive 35 ns t40a wait active duration 12 m s t41a wait inactive to cmd inactive 0 ns t42a cmd active to data read valid 90 ns t43a wait inactive to data read valid 25 ns applies to extended cycles only t44a data read valid after cmd inactive 0 ns t45a data write valid to cmd active 50 ns t46a data write valid after cmd inactive 30 ns t184a data driven from read cmd active 0 ns t185a read cmd inactive to data tri-state 30 ns 44
82595TX table 11-7. pcmcia memory access parameter description min max units comments t30b address valid to cmd active 30 ns t31b cmd inactive to address change 20 ns t34b reg inactive before cmd active 30 ns t35b reg inactive after cmd inactive 20 ns t36b ce active/inactive before cmd active 0 ns t37b ce active/inactive after cmd inactive 20 ns t38b cmd active to inactive 100 ns t39b cmd active to wait active/inactive 35 ns t40b wait active duration 12 m s t41b wait inactive to cmd inactive 0 ns t43b wait inactive to data read valid b 10 ns t44b data read valid after cmd inactive 0 ns t45b cmd active to data write valid 125 ns t46b data write valid after cmd inactive 25 ns t184b data driven from read cmd active 5 ns t185b read cmd inactive to data tri-state 100 ns 45
82595TX 281630 18 figure 11-8. pcmcia cycle 46
82595TX 11.6 local memory timings 11.6.1 dram timings the 82595TX supports up to 80 ns dram produc- ing: word transfer every 400 ns. byte transfer every 250 ns. refresh cyclee200 ns. the 82595TX supports 64 kx4or 256k x 4 dram in fast page mode only. write cycles are produced in early write mode. this eliminates using the dram oe signal (it must be connected to gnd). table 11-8. dramea.c. characteristics symbol parameter timing units notes min max t49 access time from ras 80 ns t50 access time from cas 30 ns t51 access time from column address 40 ns t52 cas to output low z 0 ns t53 output buffer turn-off delay time 0 40 ns t54 ras precharge time 75 ns t55 ras pulse width 80 ns t56 ras hold time 30 ns t57 cas to ras precharge time 20 ns t58 ras to cas delay time 30 ns t59 cas pulse width 35 ns t60 cas hold time 80 ns t61 row address set-up time 0 ns t62 row address hold time 15 ns t63 column address set-up time 0 ns t64 column address hold time 20 ns t65 column address time referenced to ras 65 ns t66 ras to column address delay time 20 ns t67 column address to ras lead time 40 ns t68 write command set-up time 0 ns t69 write command hold time 15 ns t70 write command to cas lead time 30 ns t71 d in set-up time 0 ns t72 d in hold time 15 ns t73 cas set-up time for 10 ns cas before ras refresh t74 cas hold time for cas 25 ns before ras refresh t75 fast page mode cycle time 55 ns t76 fast page mode cas precharge time 15 ns t77 random read or write cycle time 190 ns t78 ras precharge time to cas active time 100 ns 47
82595TX 281630 19 figure 11-9. dram timing diagram: fast page modeeread cycle 281630 20 figure 11-10. dram timing diagrams: fast page modeewrite cycle 281630 21 figure 11-11. dram timing diagrams: cas before ras refresh cycle 48
82595TX 11.6.2 flash/eprom timings # the 82595TX is designed to support a flash or eprom up to 200 ns access time. # the v pp signal in flash implementation is con- nected always to 12v. thus writing to the flash is controlled only by the we signal. table 11-9. flashea.c. characteristics symbol parameter min max units notes t79 address access time 200 ns t80 chip enable access time 200 ns t81 output enable access time 100 ns t82 output hold from address, ce ,oroe 0ns t84 address set-up time 0 t85 address hold time 100 ns t86 chip enable set-up time before write 15 ns t87 chip enable hold time 0 ns t88 data set-up time 60 ns t89 data hold time 15 ns 281630 22 figure 11-12. flash timingsewrite cycle 49
82595TX 281630 23 figure 11-13. flash timingseread cycle table 11-10. eeprom timings symbol description min max units comments t193 cs setup time 1.0 m s t194 sk high time 3.0 m s t195 sk low time 3.0 m s t196 cs hold time 0 m s t197 cs low time 1.0 m s t198 di setup time 0.4 m s t199 di hold time 0.4 m s t200 data out valid time 0.4 m s eeprom restriction t201 cs inactive to do floated 0.4 m s eeprom restriction 50
82595TX 281630 24 figure 11-14. eeprom timings 11.6.3 ia prom timings * the prom used is a ttl 32 x 8 bit. table 11-11. ia prom a.c. characteristics symbol parameter min max unit notes t174 address access time 60 ns t175 chip enable access time 40 ns 281630 25 figure 11-15. ia prom timings 51
82595TX 11.7 interrupt timing table 11-12. interrupt timing parameter description min max units notes t177 interrupt ack cmd inactive to irq [ 4:0 ] inactive 500 ns t178 irq [ 4:0 ] inactive to irq [ 4:0 ] active 100 ns t179 tri-state cmd inactive to irq [ 4:0 ] tri-state 500 ns 281630 26 note: for isa bus, irq is active high. for pcmcia bus, irq is active low. figure 11-16. interrupt timing 11.8 reset and smout timing general comments # both signals are asynchronous signals and have minimum pulse duration specification only. # smout during hardware power down activation. table 11-13. reset and smout timing parameter description min max units notes t180 reset minimum duration 32 ms 1 t181 smout minimum duration 100 ns 2 t182 smout activation by power down command 150 ns 3 t183 smout deactivation 25 ns 3 notes: 1. noise spikes of maximum tbd ns are allowed on reset. 2. smout is input. 3. smout is output after configuration. 281630 27 figure 11-17. smout timing 52
82595TX 11.9 jtag timing table 11-14. 82595TX jtag timing symbol parameter min max unit notes t184 tms set-up time 15 ns t185 tms hold time 10 ns t186 tdi set-up time 15 ns t187 tdi hold time 10 ns t188 input signals set-up time 15 ns t189 input signals hold time 10 ns t190 outputs valid delay 150 ns t191 tdo valid delay 40 ns t192 tck cycle time (period) 100 ns 50% duty cycle 281630 28 figure 11-18. 82595TX jtag timing 53
82595TX 11.10 serial timings table 11-15. tpe timings symbol parameter min typ max unit t 90 number of txd bit loss at start of packet 2 bits t 91 internal steady state propagation delay 400 ns t 92 internal start up delay 600 ns t 93 tdh and tdl pairs edge skew ( @ v cc /2) 1.5 3 ns t 94 tdh and tdl pairs rise/fall times 2 5 ns ( @ 0.5v to v cc b 0.5v) t 95 tdh and tdl pairs bit cell center to center 99 100 101 ns t 96 tdh and tdl pairs bit cell center to boundary 49 50 51 ns t 97 tdh and tdl pairs return to zero from last tdh 250 400 ns t 98 link test pulse width 98 100 100 ns t 99 last td activity to link test pulse 8 13 24 ms t 100 link test pulse to data separation 190 200 ns 281630 29 281630 30 figure 11-19. tpe transmit timings (link test pulse) 54
82595TX table 11-16. tpe receive timings symbol parameter min typ max unit t 105 rd to rxd bit loss at start of packet 4 19 bits t 106 rd invalid bits allowed at start of packet 1 bits t 107 rd to internal steady state propagation delay 400 ns t 108 rd to internal start up delay 2.4 m s t 109 rd pair bit cell center jitter g 13.5 ns t 110 rd pair bit cell boundry jitter g 13.5 ns t 111 rd pair held high from last valid 230 400 ns position transition 281630 31 figure 11-20. tpe receive timings (end of frame) table 11-17. tpe link integrity timings symbol parameter min typ max unit t 120 last rd activity to link fault 50 100 150 ms (link loss timer) t 121 minimum received linkbeat separation (1) 25 7ms t 122 maximum received linkbeat separation (2) 25 50 150 ms notes: 1. linkbeats closer in time to this value are considered noise and rejected. 2. linkbeats further apart in time than this value are not considered consecutive and are rejected. 55
82595TX 281630 32 figure 11-21. tpe link integrity timings table 11-18. aui timings symbol parameter min typ max unit t 126 trmt pair rise/fall times 3 5 ns t 127 bit cell center to bit cell center of 99.5 50 100.5 ns trmt pair t 128 bit cell center to bit cell boundary of 49.5 50 50.5 ns trmt pair t 129 trmt pair held at positive differential at 200 ns start of idle t 130 trtm pair return to s 40 mvp from 8.0 m s last positive transition 281630 33 figure 11-22. aui transmit timings table 11-19. aui receive timings symbol parameter min typ max unit t 135 rcv pair rise/fall times 10 ns t 136 rcv pair bit cell center jitter in preamble g 12 ns t 137 rcv pair bit cell center/boundary jitter in data g 18 ns t 138 rcv pair idle time after transmission 8 m s t 139 rcv pair return to zero from last 160 ns positive transition 56
82595TX 281630 34 figure 11-23. aui receive timings table 11-20. aui collision timings symbol parameter min typ max unit t 145 clsn pair cycle time 80 118 ns t 146 clsn pair rise/fall times 10 ns t 147 clsn pair return to zero from 160 ns last positive transition t 148 clsn pair high/low times 35 70 ns 281630 35 figure 11-24. aui collision timings table 11-21. aui noise filter timings symbol parameter min typ max unit t 152 rcv pair noise filter pulse width 25 ns accept ( @ b 285 mv) t 153 clsn pair noise filter pulse width 25 ns accept ( @ b 285 mv) 281630 36 figure 11-25. aui noise filter timings 57
82595TX table 11-22. jabber timings symbol parameter min typ max unit t 165 maximum length transmission before 20 25 150 ms jabber fault (tpe) t 166 maximum length transmission before 10 13 18 ms jabber fault (aui) t 167 minimum idle time to clear jabber function 250 275 750 ms 281630 37 figure 11-26. jabber timings table 11-23. led timings symbol parameter min typ max unit t 170 actled on time 50 450 ms t 171 actled off time 50 ms t 172 liled on time 50 ms t 173 liled off time 100 ms 281630 38 figure 11-27. led timings 58
82595TX additional 82595TX documentation this datasheet provides complete pinout and pin definitions, and electrical specifications and timings. it also includes an overview of the various subsec- tions listed in figure 1. for more complete informa- tion on the 82595TX, please ask your local sales representative for the 82595TX user manual and lan595tx specification. the 82595TX user manu- al contains detailed information on the 82595TX fea- ture set, including register descriptions and imple- mentation steps for various 82595TX functions (ini- tialization, transmission, reception). the lan595tx specification describes various hardware/software implementations and configuration techniques. hardware compatible with this interface can work with software developed by intel and other nos vendors which conform to this specification. 59

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